1. Field of the Invention
The present invention relates to a processor synthesis system and a processor synthesis method for implementing an ASIC (Application Specific Integrated Circuit), an LSI circuit designed for a specific application in digital information processing control. The implemented ASICs are used in the controllers of control apparatuses, sequence controllers of multi-media apparatuses, and controllers of household appliances,
2. Discussion of the Related Art
In the conventional ASIC, a general purpose microprocessor is built in a chip as the Central Processing Unit (CPU).
When using general purpose microprocessors, users can easily select and use microprocessors which are commercially available. In this case, however, the architectures of the microprocessors have already been fixed. The CPU bitwidths of the existing microprocessors, for example, are designed to be 2.sup.n bits including 8 bits, 16 bits, 32 bits, and the like. Accordingly, several functions of the microprocessors remain unused when the size of the control unit of the microprocessor is comparatively small and the control logic is simple and mainly focuses on the operation of addition, subtraction, and bit control. When the control logic can be implemented using the 10-bit CPU bitwidth, a 16-bit microprocessor must be used instead of a 10-bit microprocessor. It is because the bitwidths of the general purpose microprocessors have already been fixed and a 10-bit general purpose microprocessor is not available now. Thus, 6 bits of the CPU bitwidth remain unused.
The CPU bitwidth has a direct effect on the size of a chip. Consequently, the problem arises that a chip itself becomes highly redundant, because the CPU on that chip has the unused 6-bit data. In view of the aforementioned problems, a system has been desired which can synthesize the CPU having the optimal bitwidth specifically customized to perform desired functions.
The present structure for placing a CPU on an ASIC is known as a mega cell. It is called mega, because it is large. This mega cell is a microprocessor, custom designed at the transistor level in a specific ASIC technology. Present mega cell CPUs are actually microprocessors which have been designed with fixed architectures and the CPU bitwidths of 16 bits or 32 bits. Consequently, when the application requires the microprocessors other than 16-bit or 32-bit microprocessors and is moved to a new technology (or even next generation of the current technology), the mega cell must be redesigned. Since the mega cell has been designed at the transistor level, this redesign process is considerably expensive and creates schedule delay.
In view of the aforementioned problems, a system has been desired which is capable of designing the CPU at the level higher than the transistor level.
The special mega cell technology for placing a CPU on an ASIC also creates problems for system simulation and emulation, since the mega cell technology is different from the technology for fabricating the rest of the ASIC.
A module compiler is a tool for automatically creating the layout patterns of modules when the information on the functions of the modules, bit widths, and the like required for creating the layout patterns is supplied as parameters.
FIG. 35 is a block diagram showing the function of a conventional module compiler for creating the layout patterns of modules automatically. It is described on page 60-61, in the book entitled "Basic Concepts and Applications of the ASIC technology" by Masaharu Imai and the Institute of Electronics, Information and Communication Engineers of Japan, the first edition of which was published on Feb. 20, 1994.
As shown in FIG. 35, automatic module generation involves using programmed circuit netlists and programmed layout patterns of RAMs (Random Access Memory), ROM(s) (Read Only Memory), the ALU (Arithmetic Logic Unit), etc., and a technology file storing design rules. In the automatic module generation process which does not depend on a specific design technology, by altering the design technology, various layout patterns of modules can be generated, using the lines of 1.3 .mu.m, 1.0 .mu.m, or 0.8 .mu.m in width. The user should only specifies such parameters as the number of words, the bitwidth, and the like.
Next, a conventional logic synthesis system is described.
FIGS. 36 and 37 are block diagrams showing how the conventional "Tsutsuji" logic synthesis system marketed by Zuken Incorporated is used for generating a netlist.
In FIG. 36, a "Tsutsuji" 850 receives a block diagram 810 prepared by a designer using computer-aided design (CAD) systems, implements logic synthesis, and generates a netlist 860. Based on the generated netlist 860, a semiconductor chip is fabricated.
FIG. 37 shows a case where a hardware description language (HDL) is used instead of a block diagram. The hardware description language (HDL) for the "Tsutsuji" logic synthesis system is written in a logic description format (LDF). The "Tsutsuji" 850 receives an LDF 820, implements logic synthesis, and generates the netlist 860.
In the "Tsutsuji" logic synthesis system, functional components to be designed and used as input data are not necessarily restricted to those of specific manufacturers. The generated netlist can be generated in a format of a specific silicon manufacturer. Consequently, a chip which does not depend on a specific semiconductor technology can be designed.
FIGS. 38 and 39 are block diagrams of the "Retargettable Compiler System" disclosed in Japanese Unexamined Patent Application HEI3-144829.
FIG. 38 is a block diagram showing the overall configuration of the "Retargettable Compiler System".
A compiler 911 comprises syntax analysis means 912, code generation means 913, target specification and recognition means 914, target-dependent information holding means 915, and instructions expressed in an intermediate language 916. The syntax analysis means 912 receives a source program 917 and translates the source program 917 into the instructions expressed in the intermediate language 916 which is independent of a specific computer architecture. The code generation means 913 receives the instructions expressed in the intermediate language 916 and translates the instructions expressed in the intermediate language 916 into an object program 918, targeting the computer architecture recognized by the target specification and recognition means 914 and by referring to the detailed information held in the target-dependent information holding means 915. The detailed information held in the target-dependent information holding means 915 includes data on the hardware configuration and execution characteristics such as the set of machine instructions, types and numbers of registers, the data format, and the addressing system.
FIG. 39 is a block diagram showing an example of how the conventional "Retargettable Compiler System" is used.
As shown in FIG. 39, using a single compiler, the conventional "Retargettable Compiler System" can compile one source program 917 into three object programs 918a, 918b, and 918c for computer architectures 920a, 920b, and 920c respectively.
As a retargettable compiler similar to that described above, the General Purpose C Compiler (GCC) may be pointed out. The General Purpose C Compiler is a C compiler for the GNU (GNU is not UNIX) operating system. GNU refers to the computer software distributed for free by Free Software Foundation, Inc. of the U.S.A. (Refer to page 397 of the "Dictionary of New Information and Communications Terms 1996" by the Nikkei BP Publication Center, the first edition of which was published on Oct. 9, 1995.)
As public-domain software, the lcc compiler prepared by C. W. Fraser of the AT&T Bell Laboratory and D. R. Hanson of the Princeton University may be pointed out. This program is the public-domain software which is available via the Internet. The lcc compiler is a retargettable compiler whereby the instruction code of the existing processor such as SPARC, MIPS, R300, or INTEL 386 can be generated.
The compiler of the above-mentioned type, when supplied with parameters for a target computer, compiles the source program into the object program specifically matched to the architecture of the target computer. The architecture of a computer, for example, may include 8086 manufactured by Intel Corporation, MC68000 manufactured by Motorola, Incorporated, and the like. These compilers target the hardware architecture which has already been fixed. By prestoring detailed information on the fixed hardware architecture into the compiler, retargettable compilation becomes possible. Thus, when a new hardware architecture is to be determined, or a new CPU is to be designed, the compiler for the newly-designed CPU is not readily available.